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The main advantage of conducting epitaxy on the bonded template is eliminating two out of three major dislocation root causes: lattice and polarity mismatches between the substrate (e.g., Si) and the function material (e.g., InP-based Ⅲ/Ⅴ) from epitaxial growth. The thermal mismatch between the substrate and template material would still cause dislocations in the regrown materials, but it is measured to be at a significantly low level. According to the aging tests of InAs QD lasers on Si near room temperature7, a reduction in the TDD from 108 cm-2 to 106 cm-2 can extend the laser lifetime from a few months to over 100 years. It is reasonable to expect that lasers from the regrowth on the bonded template with even lower dislocation density would eliminate the defect-induced lifetime concerns for all practical applications.
It is noted that the critical thickness of InP on a SiO2/Si substrate is calculated to be 200-430 nm from a conventional model19, 22. The thickness from the interface of the bonding dielectric and InP bonding template to the observed misfit locations is ~450 nm. It is likely that the observed misfits are formed when the epitaxy thickness (including the InP template) reaches the critical thickness. Further study is expected to confirm this estimation.
Epitaxy of this thickness with such a low dislocation density promises the possibility of growing many standard Ⅲ/Ⅴ structures for electronic, photonic, and MEMS applications. In addition, we believe that this bonding plus epitaxy approach is a generic method for many other heterogeneous material combinations. The substrate could be semiconductors, dielectrics, metals, etc., and the top grown material could be bulk materials, QWs, QDs, or other nanostructures. Sequential growth on the same template can be a routine procedure to enable advanced, large wafer-scale, dense photonic integration. A good example in silicon photonics is the integration of light sources, amplifiers, modulators, and detectors on a single chip with close proximity and low coupling loss by implementing multiple selective regrowth on a single-bonding template instead of bonding three or four types of epitaxial structures on each chip11. Figure 6 schematically shows an example of the process of integrating lasers15, amplifiers23, modulators24, and photodetectors25 onto the bonding plus epitaxy integration platform. The process begins with creating passive waveguide structures on a generic substrate wafer M1, e.g., Si. Then, a one-time bonding of M2, e.g., InP, onto M1, at either the wafer scale or chips-to-wafer scale, is executed to prepare the growth template. Necessary protection and sequential regrowth for the integration of three or four types of active devices are conducted. All regrown materials must be compatible with the template for low-defect growth. Advanced regrowth techniques such as butt-joint regrowth can be applied here to maximize the integration proximity and density and minimize reflection and other undesirable effects associated with abrupt topographic change. Since compound semiconductor substrates may account for significant wafer material costs, particularly for InP substrates, our solution provides the flexibility to reuse M2 substrates, particularly for wafer-scale template transfer26. Finally, device processing in sections of different functions in the same material system can share many fabrication steps towards seamless integrated chips.
Fig. 6
Schematic of the process of integrating lasers, amplifiers, modulators, and photodetectors with the bonding plus epitaxy platformTable 1 is a qualitative comparison of the production and operation costs of the same diode laser, built using different Ⅲ/Ⅴ-on-silicon integration approaches. All costs, including the substrate material (Si and InP substrate), Ⅲ/Ⅴ epitaxy, device fabrication (bonding and device fab), chip packaging, and operation, are compared separately among the four integration approaches. The marks (x, xx, xxx) indicate the relative cost level among the four integration approaches within each column, but do not indicate the cost differences over columns. Si does not participate in the operation of a standalone Ⅲ/Ⅴ diode laser; thus, the Si/SOI substrate cost is zero for the finished Ⅲ/Ⅴ diode laser chip packaged on Si. The Si/SOI substrate cost is similar for the other three approaches since they are all able to reach sizes up to 12 inches. The additional epitaxy step to prepare a thin Ⅲ/Ⅴ template layer, which is unique in our bonding plus epitaxy approach, incurs marginal cost due to the short and simple growth. Our approach has the flexibility to reuse the Ⅲ/Ⅴ substrate26, which can further offset the additional cost from this additional template epitaxy. Therefore, the Ⅲ/Ⅴ substrate cost is similar for the three approaches using the Ⅲ/Ⅴ substrate. Considering that a 12-inch carrier in an epitaxy reactor could accommodate 24, 10, and 7 pieces of 2-, 3- and 4-inch substrate wafers, respectively, one can easily determine that the respective effective epitaxy areas for these three size wafers are 49, 54, and 72% of the full 12-inch carrier area. As a result, the Ⅲ/Ⅴ epitaxy cost is relatively high for the first and second approaches in the table since they are still limited to complex laser structure epitaxy on 2-4 inches of substrate, particularly for InP. The Ⅲ/Ⅴ epitaxy cost of our bonding plus epitaxy approach is even lower than that of the direct epitaxy on Si approach because thick buffer layers are not necessary here, which reduces the amount of epitaxy time and source material needed. The bonding cost is similar for the wafer bonding approach and the bonding plus epitaxy approach if only one type of Ⅲ/Ⅴ epitaxial structure is used. However, in the scenario of multiple Ⅲ/Ⅴ epitaxial structure integrations on the same chip, with multiple small Ⅲ/Ⅴ dies bonded onto each Si photonic chip, hundreds of Ⅲ/Ⅴ dies per Si wafer are certainly more complicated and expensive, with potentially lower yield than just bonding one large Ⅲ/Ⅴ die in each Si photonic die. Large wafer-scale chip fabrication can tremendously reduce the manufacturing costs associated with unit devices; thus, the 12-inch process should be the most cost-effective in this category. For the finished Ⅲ/Ⅴ chip packaged with the Si approach and the direct Ⅲ/Ⅴ-epitaxy-on-Si approach, the high packaging cost is due to the high-accuracy alignment needed to couple the light from a separated diode laser chip to Si photonic components. Unavoidable modal mismatch loss from this chip-to-chip optical coupling requires higher laser output power, a subsequently higher energy bill in operation and a potentially shorter lifetime. Therefore, the bonding plus epitaxy approach can be very cost competitive overall. Its high integration level and density minimizes the chip size, packaging effort, and link power budget. This allows the lasers and whole system to operate in an energy-efficient regime.
Unit laser area cost Approach Substrate material Ⅲ/Ⅴ epitaxy Fabrication Packaging Operation(energy $) Si/SOI (12 inch) InP Bonding Device fab Finished Ⅲ/Ⅴ chip packaged with Si27 None xxx (2–4 inch) xxx (2–4 inch) None xxx (3 inch) xxx xx Ⅲ/Ⅴ wafer bonding on Si28 x xxx (2–4 inch) xxx (2–4 inch) xx x (12 inch) x x Ⅲ/Ⅴ epitaxy on Si2–4 x None xx (12 inch) None x (12 inch) xxx xx Wafer bonding plus epitaxy x xxx (2–4 inch, template epitaxy included) x (12 inch) x x (12 inch) x x x low, xx medium, xxx high Table 1. Qualitative comparison of production and operation costs of the same diode laser built using different Ⅲ/Ⅴ-on-silicon integration approaches
In conclusion, we have proposed and demonstrated a special Ⅲ/Ⅴ-on-Si photonic integration platform formed by combining the benefits of both methods. We demonstrated monolithically integrated 2-μm-thick InP-based MQW laser epitaxy with a standard vertical p-i-n diode structure on the bonded InP-on-SOI substrate. The regrown epitaxy shows high material quality with significantly low dislocation density. Successful pulsed and cw lasing with good threshold current density and output power are achieved, despite incorrectly high p-type doping and fabrication imperfection. We emphasize that the bonding plus epitaxy approach is a general approach for combining different materials onto various substrates. Compared with other integration schemes, the method can be potentially cost-competitive and highly scalable, with a high integration proximity and density. By combining traditional heterogeneous and monolithic photonic integration11, 13, we can achieve large wafer-scale μm-thick Ⅲ/Ⅴ epitaxy and advanced all-in-one photonic integration for a variety of applications.